Solution of the classification task using a compartmental spiking neuron model on an FPGA

Tim T. Isakov, Alexandr V. Bakhshiev, Anton M. Korsakov

Peter the Great St. Petersburg Polytechnic University, LLC Computer Vision Systems, Russia, Saint Petersburg, Russian state scientific center for robotics and technical cybernetics (RTC)

Spike neural networks are a class of neural networks based on plausible neuron models. The spiking nature of such networks, in the presence of specialized accelerators, makes it possible to achieve energy efficiency values that are orders of magnitude higher than those of classical neural networks, which is especially important for integrating neural networks into autonomous systems. However, now such computers are not publicly available, so FPGAs are a good alternative. One of the classes of spike neuron models are segmental models. Segmental models, unlike point ones, allow one to consider the structure of a neuron, which in turn allows one to reproduce more complex dynamics of neural structures. Existing neuromorphic computers allow the implementation of only a limited set of spike models, which is also a reason for using FPGAs. Today, there is no work on hardware implementation of segmented neuron models, so this work is relevant. During the work, the approximation and hardware implementation of CSNM model (Compartmental spiking neuron model) on an FPGA was performed. To evaluate the performance of the resulting implementation, an IRIS data classifier was built. Based on the results, it was concluded that the resulting model has competitive indicators in terms of the amount of FPGA resources used, and the calculation speed is three orders of magnitude higher than on a computer. The accuracy of the resulting implementation is inferior to other works due to the use of a small number of neurons and rough approximation. Further research into approximation methods and incremental learning algorithms will improve accuracy. It is also planned to use RAM for scaling models and optimizing calculations. Another area of future work is implementing on-chip learning, both to speed up model testing and for reinforcement learning research.

spiking neural networks, classification, FPGA

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